A timing optimization method based on clock skew scheduling and partitioning in a parallel computing environment

Paper presented at the Midwest Symposium on Circuits and Systems, San Juan, Puerto Rico.This paper describes the implementation of a heuristic method to perform non-zero clock skew scheduling of digital VLSI circuits in a parallel computing environment. In the proposed method, circuit partitions that have low number of timing paths between partitions are formed. Clock skew scheduling is applied independently to each partition-sequentially or in parallel on a computing cluster-and results are iteratively merged. The scalability of the proposed method is superior compared to conventional non-zero clock skew scheduling techniques due to the reduction of analyzed circuit sizes (partition sizes) at each iteration step and the potential to parallelize the analyses of these partitions. It is demonstrated that after only the first iteration step of the proposed method, feasible clock schedules for 65% of the ISCAS'89 benchmark circuits are computed. For these circuits, average speedups of 2.1X and 2.6X are observed for sequential and parallel application of clock skew scheduling to partitions, respectively

Timing-driven physical design for VLSI circuits using resonant rotary clocking

Paper presented at the Midwest Symposium on Circuits and Systems, San Juan, Puerto Rico.Resonant clocking technologies are next-generation clocking technologies that provide low or controllable-skew, low-jitter and multi-gigahertz frequency clock signals with low power consumption. This paper describes a collection of circuit partitioning, placement and synchronization methodologies that enables the implementation of high speed, low power circuits synchronized with the resonant rotary clocking technology. Resonant rotary clocking technology inherently supports (and requires) non-zero clock skew operation, which permits further improved circuit performances. The proposed physical design flow entails integrated circuit partitioning and placement methodologies that permit the hierarchical application of non-zero clock skew system timing. This design flow is shown to be a computationally efficient implementation method

Delay insertion method in clock skew scheduling

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Linear Timing Analysis Of Soc Synchronous Circuits With Level-Sensitive Latches

This paper describes a linear programming (LP) formulation applicable to the timing analysis of large scale SOC synchronous circuits with level-sensitive latches. The proposed formulation uses a variation of the big M method [1] to modify the nonlinear constraints in the problem formulation into solvable linear constraints. By making maximum use of cycle stealing [2], operation at a higher clock frequency (reduced clock period) is possible. The industrial LP solver CPLEX [3] is used on the ISCAS'89 benchmark circuits demonstrating significant improvements in clock period

Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time . . .

This paper describes a linear programming (LP) formulation for performance optimization of large-scale, synchronous circuits with level-sensitive latches. The proposed formulation permits circuits to operate at a higher clock frequency---that is, with a lower clock period---by the application of both non-zero clock skew scheduling [7] and time borrowing [9]. This LP formulation is computationally efficient and demonstrates significant circuit performance improvement. Unlike the approach documented in [2], the LP model of the clock period minimization problem presented here is standalone and independent of the specific LP solver (solution algorithm) used. The modified big M (MBM) method is introduced and applied to the linearization of the non-linear timing constraints of level-sensitive circuits into a solvable set of fully linear constraints. Clock period improvements as large as 63% are demonstrated over conventional flip-flop based circuits with zero clock skew. These improvements are shown on the ISCAS'89 benchmark circuits by using the industrial linear solver CPLEX [1]

A single latch, high speed double-edge triggered flip-flop

Abstract — This paper describes an original circuit design of a static CMOS double-edge triggered flip-flop (DETFF). Doubleedge triggered (DET) flip-flops are bistable flip-flop circuits in which data is latched at either edge of the clock signal. Using such flip-flops permits the rate of data processing to be preserved while using lower clock frequency (as compared to a circuit with single-edge triggered flip-flops). Therefore, power consumption in DETFF based circuits may be reduced. The proposed flip-flop design has fewer transistors than other published static CMOS DETFFs. The described circuit structure is laid out in a 0  5 µm process. Circuit simulations using hspice demonstrate that the flip-flop is logically correct and functions as expected. Furthermore, the proposed design rates favorably when compared to existing static CMOS DETFF circuits. I

Demonstration Of Speed Enhancements On An Industrial Circuit

A demonstration of the application of non-zero clock skew scheduling to enhance the speed characteristics of several functional unit blocks in a high performance processor is presented. It is shown that non-zero clock skew scheduling can improve circuit performance while relaxing the strict timing constraints of the critical data paths within a high speed system. A software tool implementing a non-zero clock skew scheduling algorithm is described together with a methodology that generates the required clock signal delays by replacing clock buffers from predesigned cell libraries. Timing margin improvements of up to 18% are achieved through the application of non-zero clock skew scheduling in certain functional blocks of an industrial high performance microprocessor